At present, a lead frame is often used to provide a semiconductor chip with electrical interconnection. That is, the chip is attached to die pad of the lead frame, and then the pads on the semiconductor chip are electrically connected to leads of the lead frame using wires by way of a wire bonding technique. Thereafter, an integrated circuit comprising a semiconductor chip, a lead frame and wires is packaged using mold compound. Exposed areas of the leads are used for providing electrical interconnection from the outside to the semiconductor chip.
In order to provide good electrical interconnection with other devices, a portion of the leads must be fully exposed. If the lead area is covered with mold compound, or not fully exposed or not easily contactable, a solderability problem of the leads and a printed circuit board (PCB), for example, may arise.
In the IC package application, it has been found that, due to a lower lead stand-off or even the lack of the lead stand-off in a Quad Flat No-lead (QFN) or Power Quad Flat No-lead (PQFN) package, some circuit board level problems tend to occur, for example, the solderability is poor, and particularly, a lead short-circuit or the like is liable to occur. Increasing the lead stand-off (a projected portion of the leads with respect to the mold compound in the periphery of the leads) would be helpful for resolving the above problem.
First, referring to FIGS. 1A-1D, a conventional mold compound packaging method is described. FIGS. 1A-1D are cross-sectional views showing the current mold compound packaging process using a single-cavity mold.
FIG. 1A shows a cross-sectional view of a beforehand prepared lead frame array in which semiconductor chips 14 have been mounted and interconnects between the semiconductor chips 14 and leads 20 are performed by wires 18. The lead frame array comprises one or more lead frames 10. For convenience, FIG. 1A only schematically shows two lead frames 10, which however is not a limit in practice.
Each lead frame 10 has leads 20 and die pads 16. After the leads 20 and the die pads 16 on the lead frame 10 are formed by full-etch, edge portions of the leads 20 and/or the die pads 16 are usually further half-etched from a back surface 15 of the lead frame to form half-etched portions 12, thereby causing clearances 11 between the leads 20 and/or the die pads 16 to have an increased size on the back surface 15.
FIGS. 1A-1D only show the clearances 11 between the leads 20 and the die pads 16, but a person skilled in the art should understand that there may also exist clearances 11 between the leads 20 and between the die pads 16 (provided that a plurality of the die pads 16 are provided on one lead frame 10).
On a front surface 13 (an upper surface shown in FIG. 1A) of a lead frame array, the semiconductor chips 14 are attached to the corresponding die pads 16 respectively, and pads on the semiconductor chips 14 and the corresponding leads 20 of the lead frame 10 are connected by the wires 18.
A tape 22 is attached to the back surface 15 of the lead frame array, whereby the lead frame array structure as shown in FIG. 1A is formed, so as to be loaded into a mold for mold compound packaging.
FIG. 1B shows a process of packaging the lead frame array structure of FIG. 1A using the conventional mold compound packaging method. As shown in FIG. 1B, the currently employed mold has a single cavity 27. In the single-cavity mold, the lead frame array structure shown in FIG. 1A is disposed in a cavity 27 formed between a lower support table 28 and an upper mold chase 24 of the mold, with the front surface 13 thereof upward (a lead frame normal direction N being upward). A flow of mold compound 26 is injected into the cavity 27, until the cavity 27 is filled with the mold compound 26, thereby forming a structure as shown in FIG. 1C. As an example, the mold compound may be an epoxy mold compound (EMC).
After curing the mold compound 26 in the cavity, the lead frame array is taken out of the mold. Then, the tape 22 is removed, and a dicing/cutting process is performed.
FIG. 1D shows a partially enlarged view of the clearances 11 between the leads 20 and the die pads 16 in the structure shown in FIG. 1C. As shown in FIG. 1D, in the semiconductor IC package obtained using the conventional packaging method, the leads 20 and the die pads 16 are at substantially the same height as the mold compound 26 in the clearances 11 therebetween, thereby forming a substantially planar surface, that is, no lead stand-off is produced.
Due to the absence of lead stand-offs, the back surface 15 of the lead frame is planar. During surface mounting (attaching the packaged IC to a PCZB), it is impossible to provide a channel for redundant solder paste to smoothly flow out, and thus the redundant solder paste extends into the clearances 11 between the leads 20 and/or the die pads 16. As a result, a possibility of short-circuit between adjacent leads 20 and/or die pads 16 is increased due to the redundant solder paste.
Some methods, such as a thicker plating method and an epoxy bumping method, have been taken into consideration for solving the above problem, but these methods bring about some other problems.
In the so-called thicker plating method, a semiconductor IC package, after being formed, is thicker plated; meaning the mold compound portions are not plated, whereas additional plating is added to the lead and die pad portions to form a thicker plated layer, thereby forming a lead stand-off. However, this method has the following problems: a long plating time results in a very low UPH (Units Per Hour) in the plating process; the thicker plating process is difficult to control; in a dicing/cutting process, it is hard to perform alignment using calibration points set on the back surface of the lead frame due to the existence of the thicker plating layer; also, there exists a higher risk of whisker growing. Further, the stand-off obtained by means of the thicker plating method does not have a great height.
In the so-called epoxy bumping method, epoxy bumps are set on the back surface of the lead frame using an adhesive injection method to leave space between the lead frame and the printed circuit board, thereby causing redundant solder paste to flow out during the surface mounting process. However, in this method, besides the difficulty of controlling the co-planarity of bumps, additional equipment costs for setting epoxy bumps are increased.
In view of the above situations, there is a need for a solution that can increase lead stand-off to solve the above problems such as poor solderability, and particularly lead short-circuit, without causing a great increase of process costs.
The following are some currently existing prior-art documents in which packaging is carried out using a dual-cavity mold, but which are different from the present invention. U.S. Patent Application Publication No. US2002/0041911A1 discloses a resin encapsulation mold, which comprises an upper mold chase and a lower mold chase that form recessed portions respectively to receive a semiconductor device, and which avoids the development of air bubbles near ejection pins by adjusting the amount of protrusion of the ejection pins ejected from bottoms of the upper and lower mold clamps respectively. U.S. Pat. No. 6,746,895 discloses a method for encapsulating a multi-chip substrate array. In this method, a mold comprising an upper mold chase and a lower mold chase is used, wherein the upper mold chase has a cavity for encapsulating interconnections on a first side of a multi-chip carrier substrate, and the lower mold chase has a cavity for encapsulating the entire second side of the multi-chip carrier substrate, on which a plurality IC chips are formed. U.S. Pat. No. 6,544,816B1 discloses a method of encapsulating thin semiconductor chip-scale packages, in which upper and lower halves of a mold together form one cavity.